View 8A-250BC_6613089.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

december 2002 advance information copyright ? alliance semiconductor. all rights reserved. ? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 1 of 21 2.5v 1m x 18 pipeline d burst synchronous sram features ? organization: 1,048,576 x18 bits fast clock speeds to 250mhz in lvttl/lvcmos fast clock to data access: 2.6/2.8/3/3.4 ns fast oe access time: 2.6/2.8/3/3.4 ns fully synchronous register-to-register operation single register flow-through mode single-cycle deselect asynchronous output enable control available 100-pin tqfp and 165-ball bga packages byte write enables multiple chip enables for easy expansion 2.5v core power supply ntd? pipelined architecture available (as7c251mntd18a, as7c25512ntd32a/ as7c25512ntd36a) logic block diagram selection guide -250 -225 -200 -166 units minimum cycle time 4 4.4 5 6 ns maximum clock frequency 250 225 200 166 mhz maximum pipelined clock access time 2.6 2.8 3.0 3.4 ns maximum operating current 425 400 370 340 ma maximum standby current 110 110 110 90 ma maximum cmos standby current (dc) 70 70 70 70 ma burst logic adv adsc adsp clk lbo clk clr cs 20 18 20 a[19:0] 20 address d q cs clk register 1m 18 memory array 18 18 dqb clk dq byte write registers dqa clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down dq[a,b] 2 ce0 ce1 ce2 bw b bw a oe zz oe ft clk clk bwe gwe 18
12/2/02, v. 0.9.2 advance info alliance semiconductor 2 of 21 as7c251mpfs18a ? pin and ball designations pin configuration for 100-pin tqfp ball assignments for 165-ball bga
nc a ce0 bwb nc ce2 bwe adsc adv aa nc a ce1 nc bwa clk gwe oe adsp anc nc nc vddq vss vss vss vss vss vddq nc dqpa nc dqb vddq vdd vss vss vss vdd vddq nc dqa nc dqb vddq vdd vss vss vss vdd vddq nc dqa nc dqb vddq vdd vss vss vss vdd vddq nc dqa nc dqb vddq vdd vss vss vss vdd vddq nc dqa ft nc nc vdd vss vss vss vdd nc nc zz dqb nc vddq vdd vss vss vss vdd vddq dqa nc dqb nc vddq vdd vss vss vss vdd vddq dqa nc dqb nc vddq vdd vss vss vss vdd vddq dqa nc dqb nc vddq vdd vss vss nc vdd vddq dqa nc dqpb nc vddq vss nc a vss vss vddq nc nc nc nc a a tdi a1 1 1 a0 and a1 are the two least significant bits (lsb) of the addr ess field and set the internal burst counter if burst is desire d. tdoaaaa lbo nc a a tms a0 1 tckaaaa nc nc nc v ddq v ssq nc nc dqb dqb v ssq v ddq dqb dqb ft v dd nc v ss dqb dqb v ddq v ssq dqb dqb dqpb nc v ssq v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a nc nc v ddq v ssq nc dqa dqa dqa v ssq v ddq dq a dq a v ss zz dqa dqa v ddq v ssq dqa dqa nc nc v ssq v ddq nc nc nc lbo a a a a a1 a0 nc nc v ss v dd a a a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 nc nc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a nc vdd a tqfp 14 20 mm 1m x 18
12/2/02, v. 0.9.2 advance info alliance semiconductor 3 of 21 as7c251mpfs18a ? functional description the as7c251mpfs18a is a high-performance cmos 16-mbit synchron ous static random access memo ry (sram) device organized as 1,048,576 words x 18 bits and incorporates a two-stage register-reg ister pipeline for highest freq uency on any given technology . fast cycle times of 4/4.4/5/ 6 ns with clock access times (t cd ) of 2.6/2.8/3/3.4 ns enable 250, 225, 200, and 166 mhz bus frequencies. three chip enable (ce ) inputs permit easy memory expansion. burst operation is initiated in one of two ways: the controller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent internally generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation, the data accessed by the current address registered in the address registers by the positive ed ge of clk is carried to the data-out regi sters and driven on the output pins on the next positive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but it is sampled on all subsequent clock edges. address is incremented inte rnally for the next access of the burst when adv is sampled low and both address strobes are high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use an interleaved count sequence. with lbo driven low, the device uses a linear count sequence. write cycles are performed by disabling the output buffers with oe and asserting a write command. a global write enable gwe writes all 18 bits regardless of the state of individual bw[a,b] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signals. bwn is ignored on the clock edge that samples adsp low, but it is sampled on all subsequent clock edges. output buffers are disabled when bwn is sampled low, regardless of oe . data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . we signals are sampled on the clock edge that samples adsc low (and adsp high). master chip enable ce0 blocks adsp , but not adsc . the as7c251mpfs18a family operates from a core 2.5v power suppl y. these devices are available in a 100-pin tqfp and 165-ball bg a. tqfp and bga capacitance parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out 7pf
12/2/02, v. 0.9.2 advance info alliance semiconductor 4 of 21 as7c251mpfs18a ? signal descriptions write enable truth table (per byte) x = don?t care; l = low; h = high; b we , bwn = internal write signal signal i/o properties description clk i clock clock. all inputs except oe , ft , zz, and lbo are synchronous to this clock. a0?a17 i sync address. sampled when all ch ip enables are active and when adsc or adsp are asserted. dq[a,b] i/o sync data. driven as output when the chip is enabled and when oe is active. ce0 isync master chip enable. sampled on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the ?synchronous truth table? for more information. ce1, ce2 isync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp isync address strobe processor. asserted low to load a new bus address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe isync global write enable. asserted low to write all 32/36 and 18 bits. when high, bwe and bw[a,b] control write enable. bwe i sync byte write enable. asserted low with gwe high to enable effect of bw[a,b] inputs. bw[a,b] isync write enables. used to control wr ite of individual bytes when gwe is high and bwe is low. if any of bw[a,b] is active with gwe high and bwe low, the cycle is a write cycle. if all bw[ab] are inactive, the cycle is a read cycle. oe iasync asynchronous output enable. i/o pins are driven when oe is active and the chip is in read mode. lbo istatic count mode. when driven high, count sequence follows intel xor convention. when driven low, count sequence follows linear convention. this signal is internally pulled high. 18 tdo o sync serial data-out to the jtag circuit. delivers data on the negative edge of tck (bga only). tdi i sync serial data-in to the jtag circuit. sampled on the rising edge of tck (bga only). tms i sync this pin controls the test access port state machine. sampled on the rising edge of tck (bga only). tck o sync serial data-out to the jtag circuit. delivers data on the negative edge of tck (bga only). ft istatic flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. zz i async sleep. places device in low power mode; data is retained. connect to gnd if unused. function gwe bwe bwa bwb write all bytes (a, b) lxxx hlll write byte a h l l h write byte b h l h l read hhx x hlhh
12/2/02, v. 0.9.2 advance info alliance semiconductor 5 of 21 as7c251mpfs18a ? synchronous truth table key: x = don?t care, l = low, h = high tqfp and bga thermal resistance ce0 ce1 ce2 adsp adsc adv bwn 1 1 see ?write enable truth table? on page 4 for more information. oe address accessed clk operation dq hxxxlxxx na l to h deselecthi ? z l l x l xxxx na l to h deselect hi ? z llxhlxxx na l to h deselecthi ? z l x h l xxxx na l to h deselect hi ? z lxhhlxxx na l to h deselecthi ? z l h l l x x x l external l to h begin read hi ? z 2 2 q in flow-through mode. l h l l x x x h external l to h begin read hi ? z lhlhlxfl external l to hbegin readhi ? z 2 lhlhlxfh external l to hbegin readhi ? z x x x h h l f l next l to h continue read q x x x h h l f h next l to h continue read hi ? z x x x h h h f l current l to h suspend read q x x x h h h f h current l to h suspend read hi ? z h x x x h l f l next l to h continue read q h x x x h l f h next l to h continue read hi ? z h x x x h h f l current l to h suspend read q h x x x h h f h current l to h suspend read hi ? z lhlhlxtx external l to hbegin writed 3 3 for a write operation following a read operation, oe must be high before the input data set up time an d must be held high throughout the input hold time x x x h h l t x next l to h continue write d h x x x h l t x next l to h continue write d x x x h h h t x current l to h suspend write d h x x x h h t x current l to h suspend write d description symbol ty p i c a l units conditions thermal resistance (junction to ambient) 1 1 this parameter is sampled. 1 layer ja 40 c/w test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 4 layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 6 of 21 absolute maximum ratings note: stresses greater than those listed in this table may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside th ose indicated in the operational sections of this specification is not implied. expo sure to absolute maximum rating con- ditions may affect reliability. recommended operating conditions parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.3 +3.6 v input voltage relative to gnd (input pins) v in ?0.3 v dd + 0.3 v input voltage relative to gnd (i/o pins) v in ?0.3 v ddq + 0.3 v power dissipation p d ?1.8w dc output current i out ? 20 ma ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias t bias ?65 +135 o c parameter symbol min nominal max unit supply voltage v dd , v ddq 2.375 2.5 2.625 v v ss 0.0 0.0 0.0 input voltages address and control pins v ih 2.0 ? v dd + 0.3 v v il ?0.3 1 1 v il min = ?2.0v for pulse width less than 0.2 t rc . ?0.4 i/o pins v ih 2.0 ? v ddq + 0.3 v v il ?0.3 1 ?0.4 ambient operating temperature t a 0?70 c
12/2/02, v. 0.9.2 advance info alliance semiconductor 7 of 21 as7c251mpfs18a ? dc electrical characteristics parameter sym test conditions ?250 ?225 ?200 ?166 unit min max min max min max min max input leakage current 1 1 lbo pin has an internal pull-up, and input leakage = 10 a. |i li |v dd = max, v in = gnd to v dd ?2?2?2?2a output leakage current |i lo | oe v ih , v dd = max, v out = gnd to v dd ?11?11?11?11 a operating power supply current 2 2 i cc given with no output loading. icc increases wi th faster cycle times and greater output loading. i cc (pipelined) ce0 = v il , ce1 = v ih , ce2 = v il , f = f max , i out = 0 ma ? 425 ? 400 ? 370 ? 340 ma operating power supply current i cc (flow-through) ? 250 ? 225 ? 200 ? 175 ma standby power supply current i sb deselected, f = f max , zz v il ? 110 ? 110 ? 110 ? 90 ma i sb1 deselected, f = 0, zz 0.2v all v in 0.2v or (v dd , v ddq ) ? 0.2v ?70?70?70?70 i sb2 deselected, f = f max , zz (v dd , v ddq ) ? 0.2v all v in v il or v ih ?30?30?30?30 output voltage v ol i ol = 2 ma, v ddq = 2.65v ? 0.7 ? 0.7 ? 0.7 ? 0.7 v v oh i oh = ?2 ma, v ddq = 2.35v 1.7 ? 1.7 ? 1.7 ? 1.7 ?
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 8 of 21 timing characteristics over operating range parameter sym ?250 ?225 ?200 ?166 unit notes 1 1 see ?notes? on page 19. min max min max min max min max clock frequency f max ? 250 ? 225 ? 200 ? 166 mhz cycle time (pipelined mode) t cyc 4?4.4?5?6?ns cycle time (flow-through mode) t cycf 6.5 ? 6.9 ? 7.5 ? 8.5 ? ns clock access time (pipelined mode) t cd ? 2.6 ? 2.8 ? 3.0 ? 3.4 ns clock access time (flow-through mode) t cdf ? 6.5 ? 6.9 ? 7.5 ? 8.5 ns output enable low to data valid t oe ? 2.6 ? 2.8 ? 3.0 ? 3.4 ns clock high to output low z t lzc 0?0?0?0?ns2, 3, 4 data output invalid from clock high t oh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 2 output enable low to output low z t lzoe 0?0?0?0?ns2, 3, 4 output enable high to output high z t hzoe ? 2.6 ? 2.8 ? 3.0 ? 3.4 ns 2, 3, 4 clock high to output high z t hzc ? 2.6 ? 2.8 ? 3.0 ? 3.4 ns 2, 3, 4 output enable high to invalid output t ohoe 0? ?0?0?ns clock high pulse width t ch 1.5 - 1.8 ? 1.8 ? 2.1 ? ns 5 clock low pulse width t cl 1.5 - 1.8 ? 1.8 ? 2.2 ? ns 5 address setup to clock high t as 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6 data setup to clock high t ds 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6 write setup to clock high t ws 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6, 7 chip select setup to clock high t css 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6, 8 address hold from clock high t ah 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6 data hold from clock high t dh 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6 write hold from clock high t wh 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6, 7 chip select hold from clock high t csh 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6, 8 adv setup to clock high t advs 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6 adsp setup to clock high t adsps 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6 adsc setup to clock high t adscs 1.2 - 1.4 ? 1.4 ? 1.5 ? ns 6 adv hold from clock high t advh 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6 adsp hold from clock high t adsph 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6 adsc hold from clock high t adsch 0.3 - 0.4 ? 0.4 ? 0.5 ? ns 6
12/2/02, v. 0.9.2 advance info alliance semiconductor 9 of 21 as7c251mpfs18a ? ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). the port operates in a ccordance with ieee standard 1149.1- 1990 but does not have the set of functions requir ed for full 1149.1 compliance. the inclusion of these functions would place an added d elay in the critical speed path of the sram. the tap co ntroller functionality does no t conflict with the operation of other devices using 1 149.1 fully compliant taps. it uses jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, bo undary scan register, bypass register, and id register. disabling the jtag feature if the jtag function is not being impleme nted, its pins/balls can be left unconnecte d. at power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used with only the tap controller. all inputs ar e captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tap controller receives commands from tms input. it is sample d on the rising edge of tck. you can leave this pin/ball uncon nected if the tap is not used. the pin/ball is pulled up internally, resulting in a logic high level.

!"!!#$%&'(!()*)&
+, tap controller state diagram t ap controller block diagram $ (
( %(- $ (
( %(- . . / , , , 0%*- )(! *(&( ( )(! 0-"!! )(! !% ( )(! ,, , ,, '
+
$$ 1 2. & 3 &()%(4 1 5 & .6
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 10 of 21 test data-in (tdi) the tdi pin/ball serially inputs informatio n into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instr uction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. td i is connected to the most significant bit (msb) of any regist er. (see the tap controller block diagram.) test data-out (tdo) the tdo output pin/ball serially clocks data-out from the registers. the output is active depending upon the current state of t he tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (s ee the tap controller state diagram.) performing a tap reset you can perform a reset by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and td o pins/balls. they allow data to be scanned into and out of the sram test circuit ry. only one register can be selected at a time through the instruction regist er. data is serially loaded into the tdi pin/ball on the risin g edge of tck. data is output on the tdo pin/ball on the falling edge of tck. instruction register you can serially load three-bit instructions into the instruction register. the register is loaded when it is placed between th e tdi and tdo pins/ balls as shown in the tap controller block diagram. the instructio n register is loaded with the id code instruction at power up and also if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two leas t significant bits are loaded wi th a binary ?01? pattern to all ow for fault isolation of the board-level series test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass regi ster is a single-bit register that can be placed between the tdi and tdo pins/balls. th is allows data to be shifted through the sram with minimal de lay. the bypass register is set low (vss) wh en the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional pins/balls on the sram. the x36 configuration has a 72-bit-long register and the x18 configurat ion has a 53-bit-long register. the boundary scan register is loaded with the contents of the ra m i/o ring when the tap controller is in the capture-dr state a nd is then placed between the tdi and tdo pins/balls when the controller is moved to the shift-dr state. the extest, sample/reload, and sa mple z instructions can be used to capture the contents of the i/o ring. the boundary scan order table shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the most significant bit (msb) of the register is conne cted to tdi, and the least sign ificant bit (lsb) is connected t o tdo. identification (id) register the id register has a vendor code and other information describe d in the identification register definitions table. the id regi ster is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the i dcode is hardwired into the sram and can be shifted out wh en the tap controller is in the shift-dr state.
12/2/02, v. 0.9.2 advance info alliance semiconductor 11 of 21 as7c251mpfs18a ? tap instruction set eight different instructions are possible with the 3-bit instruct ion register. all combinations are listed in the instruction c odes table. three of these instructions are reserved and should not be used. note that the tap controller used in this sram is not fully com pliant to the 1149.1 convention because some of the mandatory 11 49.1 instructions are not fully implemented. the tap controller cannot be used to load addr ess, data, or control signals into the sr am and cannot preload the i/o buffers. the sram does no t implement the 1149.1 commands extest or intest or the preload portion of sample/ preload. instead, it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift- ir state when the instruction re gister is placed between tdi a nd tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins/balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this sram tap controller. the tap controller, however, does recognize an all-0 instruction. when an extest instru ction is loaded into the instruction reg ister, the sram responds as if a sample/preload instruction has been loaded. un like the sample/preload instruct ion, extest places the sram outp uts in a high-z state. extest is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1. idcode the idcode instruction is loaded into the instruction register up on power-up or whenever the tap controller is given a test log ic reset state. the idcode instruction causes a vendor-specific, 32-bit code to be lo aded into the instruction register. it also places the instruc tion register between the tdi and tdo pins/balls and allows the idcode to be shifted o ut of the device when the tap controller enters the shift-dr st ate. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and td o pins/balls when the tap cont roller is in a shift-dr state. it also places al l sram outputs into a high-z state. sample/preload when the sample/preload instruction is loaded into the instruction register and the ta p controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. note that the sample/preload is a 11 49.1 mandatory instruction, but the preload portion of this instruction is not implemented in this device. the tap controller, therefore, is n ot fully 1149.1 compliant. be aware that the tap controller clock can operate only at a freq uency up to 10 mhz, while the sr am clock operates more than an order of magnitude faster. because there is a large difference in the cloc k frequencies, it is possible that during the capture-dr state , an input or output can undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm t he device, but there is no guarantee as to the valu e that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long en ough to meet the tap controller?s capture se tup plus hold time ( t cs plus t ch). the sram clock input mig ht not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an is sue, it is possible to capture all other signa ls and ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bou ndary scan register between the tdi and tdo pins. note that since the preload part of the command is not impleme nted, putting the tap to the update-dr state while performing a s ample/ preload instruction will have the sa me effect as the pause-dr command. bypass the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass registe r is placed between tdi and tdo.
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 12 of 21 reserved do not use a reserved instruction.these instructions are not implemented but are reserved for future use. tap timing diagram tap ac electrical characteristics for notes 1 and 2, +10 o c < t j < +110 o c and +2.4v < v dd < +2.6v. description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 1 1 t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2 test conditions are specified using the load in the figure tap ac output load equivalent. 10 ns hold times tms hold t thmx 10 ns capture hold t ch 1 10 ns .726 '8 ' 8 8 !
$ 9 :
+; !'*$ :'; ! :; !% :; < *&(*
12/2/02, v. 0.9.2 advance info alliance semiconductor 13 of 21 as7c251mpfs18a ? tap dc electrical characterist ics and operating conditions (+10 o c < t j < +110 o c and +2.4v < v dd < +2.6v unless otherwise noted) 1. all voltage referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot: v il (ac) -0.5 for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v ddq 1.4v for t 200ms during normal operation, v ddq must not exceed v dd . control input signals (such as ld , r/w , etc.) may not have pulsed widths less than t khkl (min) or oper- ate at frequencies exceeding f kf (max). description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current outputs disabled, 0v v in v ddq (dqx) il o -5.0 5.0 a output low voltage i olc = 100 av ol1 0.2 v 1 output low voltage i olt = 2ma v ol2 0.7 v 1 output high voltage i ohs = -100 av oh1 2.1 v 1 output high voltage i oht = -2ma v oh2 1.7 v 1 input pulse levels. . . . . . . . . . . . . . . vss to 2.5v input rise and fall times. . . . . . . . . . . . . . . 1 ns input timing reference levels. . . . . . . . . . 1.25v output reference levels . . . . . . . . . . . . . . 1.25v test load termination supply voltage. . . . 1.25v tap ac test conditions tap ac output load equivalent 2 ? = 12 ? ,28 "
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 14 of 21 identification register definitions scan register sizes instruction codes instruction field 1m x 18 description revision number (31:28) xxxx reserved for version number. device depth (27:23) xxxxx defines the depth of 1mb words. device width (22:18) xxxxx defines the width of x18 bits. device id (17:12) xxxxxx reserved for future use. jedec id code (11:1) 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. register name bit size instruction 3 bypass 1 id 32 boundary scan x18:53 x36:72 instruction code description extest 000 captures i/o ring contents. places the bo undary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id c ode and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the bo undary scan register between tdi and tdo. forces all sram output dr ivers to a high-z state. reserved 011 do not use. this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the bo undary scan register between tdi and tdo. does not affect sram operation. this in struction does not impl ement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use. this instruction is reserved for future use. reserved 110 do not use. this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
12/2/02, v. 0.9.2 advance info alliance semiconductor 15 of 21 as7c251mpfs18a ? 165-ball bga boundar y scan order (x18) bit #s signal name ball id 1sa 11p 2sa 6n 3sa 8p 4sa 8r 5sa 9r 6sa 9p 7sa 10p 8sa 10r 9sa 11r 10 dqa 10m 11 dqa 10l 12 dqa 10k 13 dqa 10j 14 zz 11h 15 dqa 11g 16 dqa 11f 17 dqa 11e 18 dqa 11d 19 dqpa 11c 20 sa 11a 21 sa 10a 22 sa 10b 23 adv 9a 24 adsp 9b 25 adsc 8a 26 oe 8b 27 bwe 7a bit #s signal name ball id 28 gwe 7b 29 clk 6b 30 ce2 6a 31 bwa 5b 32 bwb 4a 33 ce1 3b 34 ce0 3a 35 sa 2a 36 sa 2b 37 dqb 2d 38 dqb 2e 39 dqb 2f 40 dqb 2g 41 ft 1h 42 dqb 1j 43 dqb 1k 44 dqb 1l 45 dqb 1m 46 dqpb 1n 47 lbo 1r 48 sa 3p 49 sa 3r 50 sa 4r 51 sa 4p 52 sa1 6p 53 sa0 6r
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 16 of 21 key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:b] is don?t care. undefined/don?t care falling input rising input t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t csh t hzc t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a1) a2 a1 a3 ce1 (pipelined mode) d out q(a2y10) q(a2y11) q(a3) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) (flow-through mode) t hzc t oe t lzoe read q(a1) suspend read q(a1) read q(a2) burst read q(a 2y01 ) read q(a3) dsel burst read q(a 2y10 ) suspend read q(a 2y10 ) burst read q(a 2y11 ) burst read q(a 3y01 ) burst read q(a 3y10 ) burst read q(a 3y11 )
12/2/02, v. 0.9.2 advance info alliance semiconductor 17 of 21 as7c251mpfs18a ? timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe data in t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d] read q(a1) suspend write d(a1) read q(a2) suspend write d(a 2 ) adv burst write d(a 2y01 ) suspend write d(a 2y01 ) adv burst write q(a 2y10 ) write d(a 3 ) burst write d(a 3y01 ) adv burst write q(a 2y11 ) adv burst write d(a 3y10 )
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 18 of 21 timing waveform of read/write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe d in d out t lzc t advh t lzoe t oe t cd q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe (pipelined mode) d out q(a1) q(a3y01) q(a3y10) (flow-through mode) t cdf q(a3y11) dsel suspend read q(a1) read q(a1) suspend write d(a 2 ) adv burst read d(a 3y01 ) suspend read q(a 3y11 ) adv burst read q(a 3y10 ) adv burst read q(a 3y11 ) read q(a2) read q(a3)
12/2/02, v. 0.9.2 advance info alliance semiconductor 19 of 21 as7c251mpfs18a ? ac test conditions notes 1 for test conditions, see ?ac test conditions?, figures a, b, and c. 2 this parameter is measured with ou tput load condition in figure c. 3 this parameter is sampled but not 100% tested. 4t hzoe is less than t lzoe , and t hzc is less than t lzc at any given temperature and voltage. 5t ch is measured as high above vih, and t cl is measured as low below vil. 6 this is a synchronous device. all addresses must meet the specified setup and hold ti mes for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all rising edges of clk when chip is enabled. 7 write refers to gwe , bwe , and bw[a,b] . 8 chip select refers to ce0 , ce1, and ce2 . z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v output load: for t lzc , t lzoe , t hzoe , t hzc , see figure c. for all others, see figure b. input pulse level: gnd to 3v. see figure a. input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. input and output timing reference levels: 1.5v. v l = v ddq /2 thevenin equivalent: 353 ?/1538? 5 pf* 319 ?/1667? d out gnd figure c: output load(b) *including scope and jig capacitance +2.5v
? as7c251mpfs18a 12/2/02, v. 0.9.2 advance info alliance semiconductor 20 of 21 package dimensions 100-pin tqfp (quad flat pack) 165-ball bga (ball grid array) he e hd d b e tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters a1 a2 l1 l c ,72>,2:62; ?,3 ?,2 6 5 3 / . 7 2 6 2 7 . / 3 5
0 ' @ + .,>, , , 2,>, 7, , 2,>, .,>, (*

= = a ,.2>,2 ,' ,6 ,2 ,= "8(b 0c8(b (*8(b ($&$*0$$ 0

0 ' @ + ,= ' '
? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and p roduct names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/o r estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant chan ges to these specifications are possible. the information in this p roduct data sheet is intended to be general descriptive information for potential customers and users, and is not intended to o perate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product describ ed herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchan tability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manu facturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. as7c251mpfs18a ? 12/2/02, v. 0.9.2 advance info alliance semiconductor 21 of 21 ordering information part numbering guide 1. alliance semiconductor sram prefix 2. operating voltage: 25 = 2.5v 3. organization: 1m 4. pipelined/flow-through mode (each device works in both modes) 5. deselect: s = single cycle deselect 6. organization: 18 = x18 7. production version: a = first production version 8. clock speed (mhz) 9. package type: tq = tqfp; b = bga 10. operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) package & width -250 h mhz ?225 mhz ?200 mhz ?166 mhz tqfp x18 as 7c251mpfs18a -250tqc as7c251mpfs18a -225tqc as7c251mpfs18a -200tqc as7c251mpfs18a -166tqc as7c251mpfs18a -225tqi as7c251mpfs18a -200tqi as7c251mpfs18a -166tqi bga x18 as 7c251mpfs18a -250bc as7c251mpfs18a -225bc as7c251mpfs18a -200bc as7c251mpfs18a -166bc as7c251mpfs18a -225bi as7c251mpfs18a -200bi as7c251mpfs18a -166bi as7c 25 1m pf s 18 a ?xxx tq or b c/i 1 23 45678 910

▲Up To Search▲

Price & Availability of 8A-250BC

	To Download 8A-250BC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .